Modern integrated circuits may be designed by combining a number of individual blocks or "cells". The functionality and design of individual cells may be predetermined and stored on a computer system as a standardized design. Such design techniques may save considerable time, as it no longer may be necessary for an integrated circuit designer to custom design each individual gate and transistor in an integrated circuit. Rather, the circuit designer may break down a new circuit design into a number of known (or new) cell designs and then combine these cells appropriately to generate a circuit design which will perform a desired function.
Once a circuit has initially been designed, it may be modeled using one or more circuit emulation programs, such as SPICE, VERILOG.TM. or VHDL. SPICE (Simulation Program with Emphasis on Circuit Emulation) is an integrated circuit emulation program developed at the University of Southern California at Berkeley which emulates performance of individual circuit elements (e.g., transistors) and may be used to emulate performance of one or more transistors in a circuit. SPICE programs are commercially available from a number of vendors. One example of a SPICE program is the HSPICE.TM. program from Meta-Software.TM., Inc., of Campbell, Calif.
VERILOG.TM. or VHDL are hardware description languages which may be used to describe, at a logic level, an integrated circuit design. Verilog-XL.TM., produced by Cadence Design Systems, Inc., of San Jose, Calif. is a software program which may emulate the performance of a circuit described using the VERILOG.TM. hardware description language. The VERILOG.TM. hardware description language is now part of IEEE standard P1364 incorporated herein by reference. The Verilog-XL.TM. program may perform a number of functions. One function, for example, may be to calculate propagation delays generated by successive gates. The Verilog-XL.TM. program may calculate such propagation delays and use such information to calculate overall propagation delays for a particular cell or group of cells.
When designing and proving an integrated circuit, it may be desirable to calculate overall power consumption and maximum power consumption for the overall circuit, as well as power consumption for individual cells. Each new design for an integrated circuit may incorporate new cell types or designs. Thus, in the prior art, in order to calculate overall short circuit current, considerable effort must be made to generate a SPICE model for each cell design, and generate suitable short circuit current models for each cell. Such modeling efforts may be time consuming and cumbersome and may increase new product development cycle times.
Short circuit current for a particular circuit element may be defined as the maximum current generated from supply voltage V.sub.DD to ground V.sub.SS. FIG. 1 illustrates an example of a well-known CMOS circuit for an inverter gate. Referring to FIGS. 1 and 2, short circuit current will be discussed.
In the embodiment of FIG. 2, a digital input signal may be input to input line 230. If the input signal on input line 230 is high, p-channel MOS transistor 240 may turn off, n-channel MOS transistor 241 may turn on, and output line 290 may go low. If the input signal on input line 230 is low, p-channel MOS transistor 240 may turn on, n-channel MOS transistor 241 may turn off, and output line 290 may go high.
The above description of FIG. 2, however, assumes ideal conditions, namely an instantaneous transfer of the input signal from a high level to a low level and vice versa. Due to propagation delays, transition from a high level voltage to a low level voltage (and vice versa) may not be instantaneous, but rather may ramp up or down over a given period of time.
FIG. 1 illustrates the three states of the inverter gate of FIG. 2 when transitioning from a low input voltage to a high input voltage. In step 110, the input voltage in input line 230 may be low, and p-channel MOS transistor 240 may be on, and n-channel MOS transistor 241 may be off. In step 120, the input voltage on input line 230 may transition from a low to high state. For a brief given instant, both p-channel MOS transistor 240 and n-channel MOS transistor 241 may both be on. In step 130, the input voltage on input line 230 may go high, and p-channel MOS transistor 240 may turn off and n-channel MOS transistor 241 may remain on.
During step 120, a short circuit may occur in the inverter circuit, as illustrated in FIG. 3. With both p-channel MOS transistor 240 and n-channel MOS transistor 241 in the on state, current may pass from supply voltage V.sub.DD line 220 through p-channel MOS transistor 240 and n-channel MOS transistor 241 to ground voltage V.sub.SS line 270. The inverter circuit of FIGS. 2 and 3 is a fundamental element in CMOS gate design, and thus, such short circuit currents may occur in other gate designs as well. The use of an inverter circuit is illustrated here by way of example only.
Depending upon the extent of propagation delays and the slope of the transition of input signals, the short circuit current of individual gates may consume considerable amounts of power. In general, the more gradual the transition from high to low level (or vice versa) the more power may be consumed by a gate, as the gate may remain in a short circuit condition for a longer period of time.
A circuit designer may wish to detect portions of an integrated circuit design with a voracious appetite for power. Once such circuit portions have been identified, step may be taken to reduce power consumption. For example, some circuit portions may be connected to further logic gates to switch such portions off when not in use. Alternatively, or in addition, the input signals to such circuit portions may be "squared up" using a buffer or the like to reduce the amount of time a circuit is in a short circuit condition.
However, as discussed above, it may be onerous to model each cell within an integrated circuit design for short circuit conditions using a SPICE type program.